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? semiconductor components industries, llc, 2011 june, 2011 ? rev. 0 1 publication order number: ncp4629/d ncp4629 500 ma, wide input range, ldo linear voltage regulator the ncp4629 is a cmos 500 ma ldo linear voltage regulator which features a high input voltage range while maintaining a low quiescent current. several protection features like current limiting and thermal shutdown are fully integrated to create a versatile and robust device. a high maximum input voltage (36 v) and wide temperature range ( ? 40 c to 105 c) makes the ncp4629 an ideal choice for high power industrial applications. features ? operating input voltage range: 4 v to 24 v ? output voltage range: 3.0 to 12.0 v (available in 0.1 v steps) ? 2% output voltage accuracy ? output current: min. 500 ma (v in = v out + 1 v) ? line regulation: 0.05%/v ? current limit circuit ? thermal shutdown circuit ? available in sot ? 89 ? 5 and dpack5 package ? these are pb ? free devices typical applications ? home appliances, industrial equipment ? cable boxes, satellite receivers, entertainment systems ? car audio equipment, navigation systems ? notebook adaptors, lcd tvs, cordless phones and private lan systems ? office equipment: copiers, printers, facsimiles, scanners, projectors, monitors vin vout ce gnd c1 c2 470 n 10 vin vout ncp4629x figure 1. typical application schematic http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 13 of this data sheet. ordering information dpak ? 5 case 369ae xx, xxx= specific device code m, mm = date code a = assembly location y = year w = work week = pb ? free package marking diagrams (*note: microdot may be in either location) sot ? 89 5 case 528ab xxx xmm 1 xxxxxxxx xx mm 1
ncp4629 http://onsemi.com 2 current limit short protection thermal shutdown vin gnd vref ce vout figure 2. simplified schematic block diagram pin function description pin no. sot89 pin no. dpack pin name description 1 1 vin input pin 2 2 gnd ground pin, all ground pins must be connected together when it is mounted on board 3 3 gnd ground pin, all ground pins must be connected together when it is mounted on board 4 4 ce chip enable pin (?h? active) 5 5 vout output pin absolute maximum ratings rating symbol value unit input voltage v in ? 0.3 to 36 v output voltage v out ? 0.3 to v in 36 v chip enable input v ce ? 0.3 to v in 36 v power dissipation sot ? 89 p d 900 mw power dissipation dpack 1900 junction temperature t j ? 40 to 150 c storage temperature t stg ? 55 to 125 c esd capability, human body model (note 2) esd hbm 2000 v esd capability, machine model (note 2) esd mm 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. duration time = 200 ms 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) latch ? up current maximum rating tested per jedec standard: jesd78.
ncp4629 http://onsemi.com 3 thermal characteristics rating symbol value unit thermal characteristics, sot ? 89 thermal resistance, junction ? to ? air r ja 111 c/w thermal characteristics, dpack thermal resistance, junction ? to ? air r ja 53 c/w electrical characteristics t a = 25 c parameter test conditions symbol min typ max unit operating input voltage v in 4 24 v output voltage v in = v out + 1 v, i out = 100 ma v out x0.98 x1.02 v output voltage temp. coefficient v in = v out + 2 v, i out = 100 a, t a = ? 40 to 105 c 100 ppm/ c line regulation v in = v out + 1 v to 24 v, i out = 10 ma line reg 0.05 0.10 %/v load regulation v in = v out + 2 v, i out = 0.1 ma to 200 ma load reg 25 60 mv dropout voltage i out = 200 ma 3.0 v v out < 5.0 v v do 0.135 0.225 v 5.0 v v out < 9.0 v 0.115 0.180 8.0 v v out 12.0 v 0.095 0.155 output current v in = v out + 1 v i out 500 ma short current limit v out = 0 v i sc 65 ma quiescent current v in = v out + 1 v, v in = v ce i q 70 130 a standby current v in = 24 v, v ce = 0 v i stb 0.1 1 a ce pin threshold voltage ce input voltage ?h? v ceh 2.0 v in v ce input voltage ?l? v cel 0 0.4 thermal shutdown temperature t sd 160 c thermal shutdown release temperature t sr 135 c power supply rejection ratio v in = v out + 2.0 v, v in_pk ? pk = 0.5 v, i out = 100 ma, f = 1 khz v out 6.0 v psrr 60 db v out > 6.0 v 50 output noise voltage v out = tbd v, i out = tbd ma, f = 10 hz to 100 khz v n tbd v rms
ncp4629 http://onsemi.com 4 typical characteristics 0 1 2 3 4 5 6 0 200 400 600 800 1000 i out , output current (ma) v out , output voltage (v) figure 3. output voltage vs. output current, v out = 5 v v in = 5.5 v 9.0 v 7.0 v 6.0 v 0 1 2 3 4 5 6 7 0 200 400 600 800 1000 1200 i out , output current (ma) v out , output voltage (v) figure 4. output voltage vs. output current, v out = 6 v v in = 6.5 v 7.0 v 8.0 v 10 v 0 2 4 6 8 10 12 14 0 200 400 600 800 1000 i out , output current (ma) v out , output voltage (v) figure 5. output voltage vs. output current, v out = 12 v v in = 12.5 v 13 v 15 v 16 v 0 1 2 3 4 5 6 012345678910 i out = 0.1 ma 100 ma 500 ma v in , input voltage (v) v out , output voltage (v) figure 6. output voltage vs. input voltage, v out = 5 v 0 1 2 3 4 5 6 7 012345678910 v in , input voltage (v) v out , output voltage (v) figure 7. output voltage vs. input voltage, v out = 6 v i out = 0.1 ma 100 ma 500 ma 0 2 4 6 8 10 12 14 03691215 v in , input voltage (v) v out , output voltage (v) figure 8. output voltage vs. input voltage, v out = 12 v i out = 0.1 ma 100 ma 500 ma
ncp4629 http://onsemi.com 5 typical characteristics 4.9 4.95 5 5.05 5.1 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) v out , output voltage (v) figure 9. output voltage vs. temperature, v out = 5 v 5.9 5.95 6 6.05 6.1 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) v out , output voltage (v) figure 10. output voltage vs. temperature, v out = 6 v 11.9 11.95 12 12.05 12.1 temperature ( c) v out , output voltage (v) figure 11. output voltage vs. temperature, v out = 12 v ? 40 ? 20 0 20 40 60 80 100 120 0 10 20 30 40 50 60 70 80 012345678910 v in , input voltage (v) supply current ( a) figure 12. supply current vs. input voltage, v out = 5 v 0 10 20 30 40 50 60 70 80 024681012 v in , input voltage (v) supply current ( a) figure 13. supply current vs. input voltage, v out = 6 v 0 10 20 30 40 50 60 70 80 0246810121416 supply current ( a) v in , input voltage (v) figure 14. supply current vs. input voltage, v out = 12 v
ncp4629 http://onsemi.com 6 typical characteristics 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 100 200 300 400 500 i out , output current (ma) dropout voltage (v) figure 15. dropout voltage vs. input current, v out = 5 v t a = 110 c 25 c ? 40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 100 200 300 400 500 t a = 110 c 25 c ? 40 c i out , output current (ma) dropout voltage (v) figure 16. dropout voltage vs. input current, v out = 6 v 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 100 200 300 400 500 i out , output current (ma) dropout voltage (v) figure 17. dropout voltage vs. input current, v out = 12 v t a = 110 c 25 c ? 40 c 0 20 40 60 80 100 120 0.1 1.0 10.0 100.0 1000 frequency (khz) psrr (db) figure 18. ripple rejection vs. frequency, v out = 5 v i out = 1 ma 100 ma 300 ma 0.1 1.0 10.0 100.0 1000 0 20 40 60 80 100 120 frequency (khz) psrr (db) figure 19. ripple rejection vs. frequency, v out = 6 v 300 ma i out = 1 ma 100 ma 0 20 40 60 80 100 120 0.1 1.0 10.0 100.0 1000 300 ma i out = 1 ma 100 ma frequency (khz) psrr (db) figure 20. ripple rejection vs. frequency, v out = 12 v
ncp4629 http://onsemi.com 7 typical characteristics frequency (khz) v n , noise density ( v rms / hz ) figure 21. output noise density, v out = 5 v 12 10 8 6 4 0 2 frequency (khz) v n , noise density ( v rms / hz ) figure 22. output noise density, v out = 6 v 0.01 0.1 1 10 100 1000 8 0.01 0.1 1 10 100 1000 7 6 5 4 3 2 1 0 v n , noise density ( v rms / hz ) frequency (khz) figure 23. output noise density, v out = 12 v 30 0.01 0.1 1 10 100 1000 25 20 15 10 5 0 4.80 4.85 4.90 4.95 5.00 5.05 5.10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 figure 24. load transient response at output current step 1 ma to 500 ma, v out = 5 v v out (v) t (ms) i out (ma) 750 500 250 0
ncp4629 http://onsemi.com 8 typical characteristics 0 250 500 750 5.80 5.85 5.90 5.95 6.00 6.05 6.10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 figure 25. load transient response at output current step 1 ma to 500 ma, v out = 6 v v out (v) t (ms) i out (ma) 0 250 500 750 11.80 11.85 11.90 11.95 12.00 12.05 12.10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 figure 26. load transient response at output current step 1 ma to 500 ma, v out = 12 v v out (v) t (ms) i out (ma) 4.97 4.98 4.99 5.00 5.01 5.02 0 40 80 120 160 200 240 280 320 360 400 150 100 50 0 v out (v) i out (ma) figure 27. load transient response at output current step 50 ma to 100 ma, v out = 5 v t ( s)
ncp4629 http://onsemi.com 9 typical characteristics 0 50 100 150 5.97 5.98 5.99 6.00 6.01 6.02 0 40 80 120 160 200 240 280 320 360 400 v out (v) i out (ma) figure 28. load transient response at output current step 50 ma to 100 ma, v out = 6 v t ( s) 0 50 100 150 11.97 11.98 11.99 12.00 12.01 12.02 0 40 80 120 160 200 240 280 320 360 400 v out (v) i out (ma) figure 29. load transient response at output current step 50 ma to 100 ma, v out = 12 v t ( s) 6 7 8 9 4.94 4.96 4.98 5.00 5.02 5.04 5.06 0 20 40 60 80 100 120 140 160 180 200 v out (v) v in (v) figure 30. line transient response, v out = 5 v t ( s)
ncp4629 http://onsemi.com 10 typical characteristics 7 8 9 10 5.94 5.96 5.98 6.00 6.02 6.04 6.06 0 20 40 60 80 100 120 140 160 180 200 v out (v) v in (v) figure 31. line transient response, v out = 6 v t ( s) 13 14 15 16 11.94 11.96 11.98 12.00 12.02 12.04 12.06 0 20 40 60 80 100 120 140 160 180 200 v out (v) v in (v) figure 32. line transient response, v out = 12 v t ( s) 0 3 6 9 ? 1 0 1 2 3 4 5 0 40 80 120 160 200 240 280 320 360 400 figure 33. turn ? on behavior with ce, v out = 5 v v out (v) t ( s) v ce (v) chip enable i out = 500 ma i out = 100 ma i out = 1 ma
ncp4629 http://onsemi.com 11 typical characteristics 0.0 3.5 7.0 10.5 ? 2 0 2 4 6 8 10 0 40 80 120 160 200 240 280 320 360 400 figure 34. turn ? on behavior with ce, v out = 6 v v out (v) t ( s) v ce (v) chip enable i out = 500 ma i out = 100 ma i out = 1 ma ? 2 0 2 4 6 8 10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 19.5 13 6.5 0 figure 35. turn ? on behavior with ce, v out = 12 v v out (v) t ( s) v ce (v) chip enable i out = 500 ma i out = 100 ma i out = 1 ma 0 3 6 9 ? 1 0 1 2 3 4 5 012345678910 v out (v) t (ms) v ce (v) figure 36. turn ? off behavior with ce, v out = 5 v chip enable i out = 500 ma i out = 100 ma i out = 1 ma
ncp4629 http://onsemi.com 12 typical characteristics 0.0 3.5 7.0 10.5 ? 2 0 2 4 6 02468101214161820 v out (v) t (ms) v ce (v) figure 37. turn ? off behavior with ce, v out = 6 v chip enable i out = 500 ma i out = 100 ma i out = 1 ma ? 3 0 3 6 9 12 0 4 8 12 16 20 24 28 32 36 40 v out (v) t (ms) v ce (v) figure 38. turn ? off behavior with ce, v out = 12 v chip enable i out = 500 ma i out = 100 ma i out = 1 ma 19.5 13.0 6.5 0
ncp4629 http://onsemi.com 13 application information a typical application circuit for ncp4629 series is shown in figure 39. vin vout ce gnd c1 c 2 470 n 10 vin vout ncp4629x figure 39. typical application schematic when vout voltage could be higher than vin voltage it is necessary to use protective diode d1. if there is possibility that vout voltage could be negative then it is necessary to use schottky diode d2. see figure 40 for details. do not force the voltage to the vout pin. vin vout ce gnd c1 c 2 470 n 10 vin vout ncp4629x d1 d2 figure 40. typical application schematic with protective diodes input decoupling capacitor (c1) a 470 nf ceramic input decoupling capacitor should be connected as close as possible to the input and ground pin of the ncp4629. higher values and lower esr improves line transient response. output decoupling capacitor (c2) a 10 f ceramic output decoupling capacitor is suf ficient to achieve stable operation of the ic. if tantalum capacitor is used, and its esr is high, the loop oscillation may result. the capacitor should be connected as close as possible to the output and ground pin. larger values and lower esr improves dynamic parameters. enable operation the enable pin ce may be used for turning the regulator on and off. the ic is switched on when a high level voltage is applied to the ce pin. the enable pin has an internal pull down current source. if the enable function is not needed connect ce pin to vin. thermal as a power across the ic increase, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and also the ambient temperature affect the rate of temperature increase for the part. when the device has good thermal conductivity through t he pcb the junction temperature will be relatively low in high power dissipation applications. the ic includes internal thermal shutdown circuit that stops operation of regulator, if junction temperature is higher than 160 c. after that, when junction temperature decreases below 135 c, the operation of voltage regulator would restart. while high power dissipation condition is, the regulator starts and stops repeatedly and protects itself against overheating. pcb layout pins number 2 and 3 must be wired to the gnd plane while it is mounted on board. make vin and gnd lines sufficient. if their impedance is high, noise pickup or unstable operation may result. connect capacitors c1 and c2 as close as possible to the ic, and make wiring as short as possible. ordering information device nominal output voltage description marking package shipping ? NCP4629HDT050T5G 5.0 v enable high c1j050b dpack ? 5 (pb ? free) 3000 / tape & reel ncp4629hdt060t5g 6.0 v enable high c1j060b dpack ? 5 (pb ? free) 3000 / tape & reel ncp4629hdt120t5g 12.0 v enable high c1j120b dpack ? 5 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *to order other package and voltage variants, please contact your on semiconductor sales representative.
ncp4629 http://onsemi.com 14 package dimensions dpak ? 5 (to ? 252, 5 lead) case 369ae ? 01 issue o dim min max millimeters e 6.40 6.80 a 2.10 2.50 b 0.40 0.60 c2 0.40 0.60 e 1.27 bsc h 9.60 10.20 l3 0.90 1.30 a1 0.00 0.13 c 0.40 0.60 e d l3 b e l 1.39 1.78 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended dimensions: millimeters 5.70 5x 10.50 6.00 2.10 0.80 1.27 pitch soldering footprint* a1 c h l detail a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. thermal pad contour optional, within dimensions b3, e2, l3 and z. 4. dimensions d and e do not include mold flash, protrusions or burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. these dimensions to be measured at datum h. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. d 5.90 6.30 a a m 0.12 c c2 c a detail a bottom view side view top view b2 5.14 5.54 e2 5.04 ref l1 2.50 2.90 l2 0.51 bsc z 2.74 ref 5x h b b2 b c e2 z l1 l2 0.10 c guage plane 2 1345
ncp4629 http://onsemi.com 15 package dimensions sot ? 89, 5 lead case 528ab ? 01 issue o mounting footprint* recommended c 0.10 top view side view bottom view c h 1 dim min max millimeters a 1.40 1.60 b1 0.37 0.57 b 0.32 0.52 c 0.30 0.50 d 4.40 4.60 d2 1.40 1.80 e 2.40 2.60 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. lead thickness includes lead finish. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. 5. dimensions l, l2, l3, l4, l5, and h are meas- ured at datum plane c. e 1.40 1.60 l 1.10 1.50 h 4.25 4.45 l2 0.80 1.20 l3 0.95 1.35 l4 0.65 1.05 l5 0.20 0.60 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. d e a c 23 54 l l5 e e b b1 l2 d2 l4 l3 2x 0.62 dimensions: millimeters 1 2x 1.50 1.30 2.79 0.45 1.50 1.65 4.65 4x 0.57 1.75 1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp4629/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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